1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including a reference circuit composed of transistors, each having a floating gate, which are used to form a sense amplifier having different threshold levels. More particularly, this invention is concerned with a flash memory requiring many reference levels for realizing complex functions.
2. Description of the Related Art
As far as flash memories are concerned, high circuit integration is facilitated due to the introduction of microscopic cells but this means that it is becoming more difficult to guarantee the reliability of the data. A plurality of reference levels, that change little from one another, are set so that reliability can be guaranteed through each of verification after writing (changing a logical state from 1 to 0) and verification after erasure (changing a logical state from 0 to 1). The reference levels are selected according to the operation to be performed.
A sense amplifier is widely adopted in order to read data not only from a flash memory but also from a memory cell. Sense amplifiers are broadly divided into two types, that is, a type of identifying data of 0 or 1 using a level set in a sense amplifier itself as a reference, and a type of identifying data by comparing it with the contents of a reference cell for generating a reference. The type in which a level is set in a sense amplifier is adopted when the level representing 0 and the level representing 1 are fully separated from each other and all that is required is to identify the level representing 0 or 1. In contrast, the type in which a reference cell is used to produce a reference has the advantage that any level can be generated by adjusting a level set in the reference cell, though the circuitry is complex and the manufacturing process is complex because the reference cell must be brought to a given state. At present, the type in which a reference cell is used has become the most popular. In particular, when a plurality of reference levels must be set as mentioned above, a type in which reference cells having a plurality of different levels set therein are used is adopted. A plurality of reference cells associated with reading, writing verification, and erasure verification are included.
A plurality of reference cells are required to have the currents flowing along channels thereof set to different given values. For differentiating the channel currents, various methods are available. In the past, a transistor having a floating gate was used to form a reference cell as it is used to form a memory cell included in a flash memory. An amount of charge to be injected into the floating gate is set in the testing stage in the process of manufacturing, whereby the channel current of the reference cell is adjusted to have a given value exactly. With regard to the injection of charge into the floating gate, injection of charge and measurement of a channel current are carried out repeatedly, the same number of times as the number of transistors, in the testing stage in the process of manufacturing. Thus, the channel currents of the transistors are set to given values.
In a known reference cell circuit, the same number of transistors as the number of reference levels are included independently, and the channel currents of the transistors are set independently. For setting the channel currents, it is necessary to carry out injection of charge and measurement of a channel current repeatedly the same number of times as the number of transistors. This poses a problem in that much time is required for testing and the cost increases.
In recent years, flash memory, and the like, has been required to attain more precise control in line with higher circuit integration and the number of reference levels has tended to increase. Moreover, one memory cell has stored data of one bit in the past. Studies have been made on storage of multivalued data in one memory cell. If the occasion arises, the number of reference levels would increase markedly. This being the case, when the number of reference cells is increased and the cells must be set to given channel currents, a great increase in testing time is predicted.